FIG. 5 is a plan view showing an example of pin arrangement of a BGA (Ball Grid Array) package substrate. FIG. 5 shows a solder-ball(electrode)-attached surface of a substrate 100 of a 144 (12×12)-pin BGA package with a 0.8-mm ball pitch (just referred to as a “substrate” as well) for a 64M/128M bit (×32) DDR (Double Data Rate) SDRAM (Synchronous DRAM)/SGRAM (Synchronous Graphic DRAM) defined by the JEDEC (Joint Electron Device Engineering Council).
Four sets of terminals (pins) for data signals are arranged in regions 3-1, 3-2, 3-3, and 3-4 on three sides of the substrate 100 on a peripheral side, respectively. Each set of the terminals is constituted from eight DQ terminals (DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, or DQ24 to DQ31) for performing input and output of data signals of eight bits, a DQS terminal for performing input and output of a data strobe signal, and a DM terminal for performing input of a DQ write mask signal. In a region 2 on a lower side of FIG. 5, command/address terminals (pins) constituted from the terminals for control signals of a differential pair of clock signals (CK, CKB), a clock enable signal (CKE), a chip select signal (CSB), a row address strobe signal (RASB), a column address strobe signal (CASB), a write enable signal (WEB), address signals (A0 to A11), and bank select signals (BA0, BA 1) are provided. In an internal region, terminals for power supplies VDD/VSS and VDDQ/VSSQ, and a reference voltage VREF are arranged. Power supplies VDDQ and VSSQ are an I/O buffer high-potential power supply and an I/O buffer low-potential power supply, respectively.
FIG. 6 is a plan view showing a typical example of a surface (a chip-mounted surface) of the substrate 100 in a state where a 64M/128M bit (×32) DDR DRAM chip 10 has been placed on the substrate 100 and wire bonding has been performed on the substrate 100. As shown in FIG. 6, four memory cell arrays 14 are provided, and four sets of pad regions 13-1 and 13-3 and pad regions 13-2 and 13-4 for the data signals are arranged on both longitudinal sides of the rectangular chip 10. Pad regions 12-1 and 12-2 for command/address signals are also disposed on the both longitudinal sides of the rectangular chip 10.
An array of bond fingers 6 is aligned and arranged on each of right and left sides of the surface of the substrate 100, with each bond finger corresponding to each pad 11 of the chip 10. The pad 11 of the chip 10 is electrically connected to a corresponding bond finger 6 on the surface of the substrate 100 by a bonding wire 7. As schematically shown in FIG. 8, a printed substrate formed of two conductive layers with a dielectric layer (insulating layer) interposed therebetween is employed as this substrate 100. Then, on a surface opposite to the chip-mounted surface, there is provided a land 102 with a solder ball 101 placed thereon. The land 102 on a surface opposite to the chip-mounted surface of the substrate 100 is electrically connected to the chip-mounted surface via a through hole 103 and connected to a corresponding one of the bond fingers 6. As shown in FIG. 8, the chip-mounted surface of the semiconductor device is sealed by an insulating resin (a sealing resin) 9.
In a semiconductor device, as shown in FIG. 6, the pads 11 on the chip 10 are arranged on both of right and left sides of the chip 10, respectively, and corresponding to the arrangement of the pads 11, the bond fingers 6 are aligned and arranged on both of right and left sides of the surface of the substrate 100, respectively.
FIG. 7 shows a reference example of superimposed layouts of two layers of the chip-mounted surface and an electrode-mounted surface of the substrate 100. FIG. 7 illustrates wiring (interconnection) patterns, each extending from the land for solder-ball 102 on the back side of the substrate to the bond finger 6 on the surface of the substrate via a through hole 103. Referring to FIG. 7, reference numeral 102 denotes the land for solder-ball on the back side of the substrate 100, reference numeral 103 denotes the through hole that electrically connects the back side of the substrate to the surface of the substrate, reference numeral 104 denotes a wiring pattern extending from a through hole land on the surface of the substrate to the bond finger 6, and reference numeral 105 denotes a wiring pattern extending from the land for solder-ball 102 on the back side of the substrate to the through hole land on the back side. Reference numerals 3-1, 3-2, 3-3, and 3-4 denotes regions for arranging four sets of terminals for the data signals (corresponding to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, and DQ24 to DQ31 in FIG. 5, respectively). Reference numeral 2 denotes a terminal region for the command/address.
As shown in FIG. 7, referring to signal wiring for data signals in each of the regions 3-1 to 3-4, the signal wiring is once led out from the land for solder-ball 102 on the back side of the substrate in a diagonally lateral direction in FIG. 7 via the wire (conductive layer pattern) 105, connected to the through hole 103, and led out to the surface (chip-mounted surface) of the substrate, and is connected to the corresponding bond finger 6 among the bond fingers 6 aligned on either side of the substrate, via the wire (conductive layer pattern) 104.
As shown in FIG. 7, according to a distance between the land for solder-ball 102 on the back side of the substrate and the corresponding bond finger 6 on the surface of the substrate, an approximate wiring length is determined.
Then, as shown in FIG. 7 as well, it can be seen that a difference between maximum and minimum values of wiring lengths for the data signals is large. Specifically, on the back side of the substrate, no significant difference of a length of the wire 105 between the land for solder-ball 102 and the through hole land is recognized (among the regions 3-1 to 3-4). However, a difference of a length of the wire 104 from the through hole land on the surface (chip-mounted-surface) of the substrate to the bond finger 6 is large (among the regions 3-1 to 3-4). A ratio of the maximum value of the length of the wiring between the land for solder-ball 102 and the bond finger 6 in the regions 3-1 and 3-4 to the minimum value of the length of the wiring between the land for solder-ball 102 and the bond finger 6 in the regions 3-2 and 3-3 amounts even close to a digit (10 times), exceeding several times, for example.
Such non-uniformity in the wiring lengths is caused by constraints such as a relationship between assignment of the pins (solder balls) shown in FIG. 5 and arrangement of the pads on the chip 10 in FIG. 6 and the two-layered substrate. That is, one array of the bond fingers 6 is disposed in either side on the chip-mounted surface of the substrate 100. Since a density of wires 104 led out in a lateral direction (a direction orthogonal to a direction in which the bond fingers 6 are arranged) is relatively high, there is no allowance for expanding a space between the bond fingers 6. Accordingly, a sufficient space for adjusting a wiring length is no longer left. The extremely short wire 104 connected to the bond finger 6, which is connected to the land 102 via the through hole 103 in each of the regions 3-2 and 3-3 shows that it is the only way to enable wiring. In other words, in view of an arrangement relationship between the adjacent bond fingers 6, no extra layout space for extending the wire 104 is left.
Even if a difference between the maximum and minimum values of the wiring lengths for data (DQ) signals in a package is as shown in FIG. 7, a difference among propagation delay times of the signals is on the order of picoseconds. When the semiconductor device is not applied to achieve a high-speed transfer rate, the difference among the propagation delay times of the DQ signals will not manifest itself as a problem. However, in a DDR DRAM with a transfer rate of several hundred MHz, for example, uniformity in the wiring lengths for the DQ signals in the package is desired.
Further, as a support for a faster operation of the DDR DRAM, enhancement of the power supplies VDD/VSS and VDDQ/VSSQ in the DQ signals is required. More specifically, power supply pads are disposed in each of the pad regions 13-1 to 13-4 of the chip in FIG. 6, and are wire bonded to the corresponding bond fingers 6, respectively. Enhancement of the power supplies VDD/VSS and VDDQ/VSSQ of the DQ signals means an increase in the number of the bond fingers 6 for the power supplies. No free region for adding another additional bond fingers to the arrays of the bond fingers 6 is left so as to achieve this purpose.